1. Field of the Invention
The present invention relates to a semiconductor circuit element device with an arrangement for testing the device and a method of testing the state of connection between external pins of the device and conductor connecting portions on a printed circuit board.
The device and method according to the present invention are applicable to the test of a semiconductor circuit element device mounted on a printed circuit board by surface mount technology (SMT).
2. Description of the Related Art
In surface mount technology (SMT), a large-scale integrated circuit (LSI) is mounted on an SMT type printed circuit board by soldering surface mount device type lead conductors of the LSI to "foot prints", or conductor connecting portions, provided on the board. Since it is possible to mount LSI's on both sides of a printed circuit board by surface mount technology, the density of LSI's on the board is increased.
When mounting semiconductor circuit element devices on a printed circuit board by surface mount technology, there are frequent failures of soldering of the lead conductors of the devices to the "foot prints". Accordingly, it is necessary to test the manufactured semiconductor circuit element devices with the printed circuit board.
Recently, along with the increase of the number of the gates of LSI's, the number of the lead conductors of LSI's has increased. The difficulty of the above test has increased accordingly.
In order for the prior art in-circuit tester for semiconductor circuit element devices to handle surface mount device type LSI's having an increased number of lead conductors, such as LSI's of the small outline package (SOP) type or the quad flat package (QFP) type, the tester would have to be made much more complex, making it expensive.
Returning to the above test, failure of soldering of the lead conductors of semiconductor circuit element devices to the "foot prints" on the printed circuit board is detected by supplying test pattern signals to the devices through a probe pin through probe points on the devices connected to input pins, picking up pattern signals which are processed by a system circuit in devices in correspondence with supplied test pattern signals, from the devices through a probe pin through probe points on the devices connected to output pins, comparing the supplied test pattern signals and the picked processed pattern signals. The failure of soldering is determined based on the comparison of the signals.
However, as the number of the gates of the devices increases, the work of making the test pattern necessary for the test tends to be more time-consuming and elaborate, so the testing of manufactured semiconductor circuit element devices becomes difficult. In view of the increase of the kinds of LSI's developed and the reduction of the life of LSI products, the above-mentioned difficulty is beginning to be considered a serious obstacle.